Technical Field
The present disclosure relates to a method of manufacturing a semiconductor device.
Related Art
Conventionally, a technique of forming a p-type semiconductor region on group-III nitride semiconductor, such as gallium nitride (GaN), through ion implantation has been known. Japanese Patent Laid-Open Nos. 2004-356257 and 2016-181580, and Japanese Patent No. 5358955 describe methods of ion-implanting p-type impurities into a semiconductor layer and subsequently applying thermal annealing in order to recover the crystalline nature in the ion-implanted region, as a method of forming a p-type semiconductor region.
Conventionally, a technique of forming a p-type semiconductor region on group-III nitride semiconductor, such as gallium nitride (GaN), through ion implantation has been known. Japanese Patent Laid-Open Nos. 2004-356257 and 2016-181580, and Japanese Patent No. 5358955 describe methods of ion-implanting p-type impurities into a semiconductor layer and subsequently applying thermal annealing in order to increase the hole concentration, as methods of forming a p-type semiconductor region.
Unfortunately, in general, degradation in crystalline nature due to ion implantation is severe. The conventional methods have a possibility that the degradation in crystalline nature in the ion-implanted region cannot be sufficiently recovered even after the thermal annealing. There is another problem in that incapability of sufficiently recovering from the degradation in crystalline nature in the ion-implanted region increases the leakage current in the semiconductor device. Accordingly, a method of sufficiently recovering from degradation in crystalline nature in the ion-implanted region has been required.
The formation of the p-type semiconductor region through ion implantation possibly causes a problem that the roughness of the surface of the ion-implanted semiconductor layer negates atomic steps on the surface of the semiconductor layer. This negation possibly degrades the crystalline nature of a semiconductor layer to be formed on the existing semiconductor layer. The application of the thermal annealing separates some constituent atoms of the semiconductor layer on the surface of the semiconductor layer, thereby possibly forming holes (hereinafter called “pits”) on the semiconductor layer. The pits possibly rough the surface of the semiconductor layer and reduce the hole concentration. Accordingly, a method is required that increases the hole concentration while preventing the atomic steps on the surface of the semiconductor layer from being eliminated, and prevents pits in the semiconductor layer from being formed.